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freescale semiconductor technical data ? 2010 freescale semiconductor, inc. all rights reserved. this document provides an overview of the mpc8323e powerquicc ii pro processor features. the mpc8323e is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including adsl soho and residential gateways, modem/routers, industr ial control, and test and measurement applications. the mpc8323e extends current powerquicc offerings, adding higher cpu performance, additional functiona lity, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate. this document describes the mpc8323e, and unless otherwise noted, the information also applies to the mpc8323, mpc8321e, and mpc8321. to locate published errata or updates for this document, refer to the mpc8323e product summary page on our website listed on the back cover of this document or contact your local freescale sales office. document number: mpc8323eec rev. 4, 09/2010 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 6 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. ddr1 and ddr2 sdram . . . . . . . . . . . . . . . . . . . . 13 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. ethernet and mii management . . . . . . . . . . . . . . . . . 19 9. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15. ipic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 17. tdm/si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18. utopia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 19. hdlc, bisync, transparent, and synchronous uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 20. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 21. package and pin listings . . . . . . . . . . . . . . . . . . . . . 49 22. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 23. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24. system design information . . . . . . . . . . . . . . . . . . . 76 25. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 79 26. document revision history . . . . . . . . . . . . . . . . . . . 80 mpc8323e powerquicc ii pro integrated communications processor family hardware specifications
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 2 freescale semiconductor overview 1overview the mpc8323e incorporates the e300c2 (mpc603e-based) core built on power architecture? technology, which includes 16 kbytes of l1 instruc tion and data caches, dual integer units, and on-chip memory management units (mmus). the e300c2 core does not contain a floating point unit (fpu). the mpc8323e also includes a 32-bit pci controller, four dma channels, a security engine, and a 32-bit ddr1/ddr2 memory controller. a new communications complex based on quicc engi ne technology forms the heart of the networking capability of the mpc8323e. the quicc engine block contains several peripheral controllers and a 32-bit risc controller. protocol support is provide d by the main workhorses of the device?the unified communication controllers (uccs). note that the mpc8321 and mpc8321e do not support utopia. a block diagram of the mpc8323e is shown in figure 1 . figure 1. mpc8323e block diagram each of the five uccs can support a variety of co mmunication protocols: 10/100 mbps ethernet, serial atm, hdlc, uart, and bisync?and, in the mpc8323e and mpc8323, multi-phy atm and atm support for up to oc-3 speeds. local baud rate generators parallel i/o accelerators single 32-bit risc cp 3 mii/rmii 4 tdm ports 1 ul2/8-bit quicc engine block security engine (sec 2.2) pci ddr ucc4 ucc3 ucc2 ucc1 multi-user ram serial dma and 2 virtual dmas serial interface ucc5 spi time slot assigner spi mpc8323e usb system interface unit (siu) system reset clock synthesizer protection and configuration interrupt controller 4 channel dma bus arbitration duart i 2 c pci controller local bus memory controllers gpcm/upm 32-bit ddr1/ddr2 interface unit timers, power management, and jtag/cop 16 kb d-cache 16 kb i-cache e300c2 core integer unit (iu1) integer unit (iu2) classic g2 mmus
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 3 overview note the quicc engine block can also support a utopia level 2 capable of supporting 31 multi-phy (mpc8323e- and mpc8323-specific). the mpc8323e security engine (sec 2.2) allows cp u-intensive cryptographic operations to be offloaded from the main cpu core. the security-processing accelerator provides hardware acceleration for the des, 3des, aes, sha-1, and md-5 algorithms. in summary, the mpc8323e family provides users with a highly integrated, fully programmable communications processor. this helps ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new st andards and evolving system requirements. 1.1 mpc8323e features major features of the mpc8323e are as follows: ? high-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for atm or ip/ethernet packet processing (or both). ? mpc8323e quicc engine block offers a future-proof solution for next generation designs by supporting programmable protocol termination and ne twork interface termina tion to meet evolving protocol standards. ? single platform architecture supports the convergence of ip packet networks and atm networks. ? ddr1/ddr2 memory controller?one 32-bit interface at up to 266 mhz supporting both ddr1 and ddr2. ? an e300c2 core built on power architecture technol ogy with 16-kbyte instruction and data caches, and dual integer units. ? peripheral interfaces such as 32-bit pci (2.2) interface up to 66-mhz operation, 16-bit local bus interface up to 66-mhz operation, and usb 2.0 (full-/low-speed). ? security engine provides acceleration for c ontrol and data plane security protocols. ? high degree of software compatibility with previous-generation powerquicc processor-based designs for backward compatibility and easier software migration. 1.1.1 protocols the protocols are as follows: ? atm sar up to 155 mbps (oc-3) full duplex, with atm traffic shaping (atf tm4.1) ? support for atm aal1 structured and unstructured circuit emulation service (ces 2.0) ? support for ima and atm transmission convergence sub-layer ? atm oam handling features compatible with itu-t i.610 ? ip termination support for ipv4 and ipv6 packets including tos, ttl, and header checksum processing ? extensive support for atm statistics and ethernet rmon/mib statistics ? support for 64 channels of hdlc/transparent
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 4 freescale semiconductor overview 1.1.2 serial interfaces the mpc8323e serial interfaces are as follows: ? support for one ul2 interface with 31 multi-phy addresses (mpc8323e and mpc8323 only) ? support for up to three 10/100 mbps ethernet interfaces using mii or rmii ? support for up to four t1/e1/j1/e3 or ds-3 serial interfaces (tdm) ? support for dual uart and spi interfaces and a single i 2 c interface 1.2 quicc engine block the quicc engine block is a versatile communications co mplex that integrates several communications peripheral controllers. it provides on-chip system de sign for a variety of applications, particularly in communications and networking systems. the qui cc engine block has the following features: ? one 32-bit risc controller for flexible support of the communications peripherals ? serial dma channel for receive and transmit on all serial channels ? five universal communication controllers (u ccs) supporting the following protocols and interfaces (not all of them simultaneously): ? 10/100 mbps ethernet/ieee 802.3? standard ? ip support for ipv4 and ipv6 packets including tos, ttl, and header checksum processing ? atm protocol through utopia interface (note that the mpc8321 and mpc8321e do not support the utopia interface) ? hdlc /transparent up to 70-mbps full-duplex ? hdlc bus up to 10 mbps ? asynchronous hdlc ? uart ? bisync up to 2 mbps ? quicc multi-channel controller (qmc) for 64 tdm channels ? one utopia interface (upc1) supporting 31 multi-phys (mpc8323e- and mpc8323-specific) ? two serial peripheral interfaces (spi). spi 2 is dedicated to ethernet phy management. ? four tdm interfaces ? thirteen independent baud rate generators and 19 input clock pins for supplying clocks to ucc serial channels ? four independent 16-bit timers that can be interconnected as two 32-bit timers the uccs are similar to the powerquicc ii peripherals: scc (bisync, uart, and hdlc bus) and fcc (fast ethernet, hdlc, transparent, and atm).
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 5 overview 1.3 security engine the security engine is optimized to handle all the algorithms associated with ipsec, ieee 802.11i? standard, and iscsi. the security engine contains one crypto-channel, a controller, and a set of crypto execution units (eus). the execution units are: ? data encryption standard execution unit (deu), supporting des and 3des ? advanced encryption standard unit (aesu), supporting aes ? message digest execution unit (mdeu), supporting md5, sha1, sha-256, and hmac with any algorithm ? one crypto-channel supporting multi-command descriptor chains 1.4 ddr memory controller the mpc8323e ddr1/ddr2 memory controller includes the following features: ? single 32-bit interface supporting both ddr1 and ddr2 sdram ? support for up to 266-mhz data rate ? support for two 16 devices ? support for up to 16 simultaneous open pages ? supports auto refresh ? on-the-fly power management using cke ? 1.8-/2.5-v sstl2 compatible i/o ? support for 1 chip select only ? fcram, ecc, hardware/software calibration, bit deskew, qin stage, or atomic logic are not supported. 1.5 pci controller the mpc8323e pci controller includes the following features: ? pci specification revision 2.3 compatible ? single 32-bit data pci interface operates up to 66 mhz ? pci 3.3-v compatible (not 5-v compatible) ? support for host and agent modes ? on-chip arbitration, supporting three external masters on pci ? selectable hardware-enforced coherency 1.6 programmable interrupt controller (pic) the programmable interrupt controller (pic) implement s the necessary functions to provide a flexible solution for general-purpose interrupt control. th e pic programming model is compatible with the mpc8260 interrupt controller, and it supports 8 extern al and 35 internal discrete interrupt sources. interrupts can also be redirected to an external interrupt controller.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 6 freescale semiconductor electrical characteristics 2 electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8323e. the mpc8323e is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.26 v ? pll supply voltage av ddn ?0.3 to 1.26 v ? ddr1 and ddr2 dram i/o voltage gv dd ?0.3 to 2.75 ?0.3 to 1.98 v? pci, local bus, duart, system control and power management, i 2 c, spi, mii, rmii, mii management, and jtag i/o voltage ov dd ?0.3 to 3.6 v ? input voltage ddr1/ddr2 dram signals mv in ?0.3 to (gv dd + 0.3) v 2 ddr1/ddr2 dram reference mv ref ?0.3 to (gv dd + 0.3) v 2 local bus, duart, clkin, system control and power management, i 2 c, spi, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 3 pci ov in ?0.3 to (ov dd + 0.3) v 5 storage temperature range t stg ?55 to 150 c? notes: 1. functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 7 electrical characteristics 2.1.2 power supply voltage specification table 2 provides the recommended operating conditions for the mpc8323e. note that these values are the recommended and tested operating c onditions. proper device operation outside of these conditions is not guaranteed. figure 2 shows the undershoot and overshoot voltages at the interfaces of the mpc8323e figure 2. overshoot/undershoot voltage for gv dd /ov dd table 2. recommended operating conditions 3 characteristic symbol recommended value unit notes core supply voltage v dd 1.0 v 50 mv v 1 pll supply voltage av dd 1.0 v 50 mv v 1 ddr1 and ddr2 dram i/o voltage gv dd 2.5 v 125 mv 1.8 v 90 mv v1 pci, local bus, duart, system control and power management, i 2 c, spi, and jtag i/o voltage ov dd 3.3 v 300 mv v 1 junction temperature t a /t j 0 to 105 c2 note: 1. gv dd , ov dd , av dd , and v dd must track each other and must vary in the same direction?either in the positive or negative direction. 2. minimum temperature is specified with t a ; maximum temperature is specified with t j . 3. all io pins should be interfaced with peripherals operating at same voltage level. 4. this voltage is the input to the filter discussed in section 24.2, ?pll power supply filtering ? and not necessarily the voltage at the avdd pin, which may be reduced due to voltage drop across the filter. gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/ov dd + 20% g/ov dd g/ov dd + 5% of t interface 1 1. t interface refers to the clock period associated with the bus clock interface. v ih v il note:
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 8 freescale semiconductor electrical characteristics 2.1.3 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 2.1.4 input capacitance specification table 4 describes the input capacitance for the clkin pin in the mpc8323e. 2.2 power sequencing the device does not require the core supply voltage (v dd ) and io supply voltages (gv dd and ov dd ) to be applied in any particular order. note that duri ng power ramp-up, before the power supplies are stable and if the i/o voltages are supplied before the core vol tage, there might be a period of time that all input and output pins are actively driven and cause contenti on and excessive current. in order to avoid actively driving the i/o pins and to eliminate excessive current draw, apply the core voltage (v dd ) before the i/o voltage (gv dd and ov dd ) and assert poreset before the power supplies fully ramp up. in the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the i/o supplies reach 0.7 v; see figure 3 . once both the power supplies (i/o voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating poreset . note that there is no specific power down sequence requirement for the device. i/o voltage supplies (gv dd and ov dd ) do not have any ordering requireme nts with respect to one another. table 3. output drive capability driver type output impedance ( ) supply vo l ta g e local bus interface utilities signals 42 ov dd = 3.3 v pci signals 25 ddr1 signal 18 gv dd = 2.5 v ddr2 signal 18 gv dd = 1.8 v duart, system control, i2c, spi, jtag 42 ov dd = 3.3 v gpio signals 42 ov dd = 3.3 v table 4. input capacitance specification parameter/condition symbol min max unit notes input capacitance for all pins except clkin c i 68pf? input capacitance for clkin c iclkin 10 ? pf 1 note: 1. the external clock generator should be able to drive 10 pf.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 9 power characteristics figure 3. mpc8323e power-up sequencing example 3 power characteristics the estimated typical power dissipation for this family of mpc8323e devices is shown in table 5 . table 6 shows the estimated typical i/o power dissipation for the device. table 5. mpc8323e power dissipation csb frequency (mhz) quicc engine frequency (mhz) core frequency (mhz) typical maximum unit notes 133 200 266 0.74 1.48 w 1, 2, 3 133 200 333 0.78 1.62 w 1, 2, 3 notes: 1. the values do not include i/o supply power (ov dd and gv dd ) or av dd . for i/o power values, see ta ble 6 . 2. typical power is based on a nominal voltage of v dd = 1.0 v, ambient temperature, and the core running a dhrystone benchmark application. the measurements were taken on the mpc8323mds evaluation board using wc process s ilicon. 3. maximum power is based on a voltage of v dd = 1.07 v, wc process, a junction t j = 110 c, and an artificial smoke test. table 6. estimated typical i/o power dissipation interface parameter gv dd (1.8 v) gv dd (2.5 v) ov dd (3.3 v) unit comments ddr i/o 65% utilization 2.5 v r s = 20 r t = 50 1 pair of clocks 266 mhz, 1 32 bits 0.212 0.367 ? w ? t 90% v core voltage (v dd ) i/o voltage (gv dd and ov dd ) 0 0.7 v poreset >= 32 clocks x t sys_clk_in /t pci_sync_in
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 10 freescale semiconductor clock input timing note av dd n (1.0 v) is estimated to cons ume 0.05 w (under normal operating conditions and ambient temperature). 4 clock input timing this section provides the clock input dc and ac electrical characteristics for the mpc8323e. note the rise/fall time on quicc engine input pins should not exceed 5 ns. this should be enforced especially on clock signals. rise time refers to signal transitions from 10% to 90% of vcc; fall time refers to transitions from 90% to 10% of vcc. 4.1 dc electrical characteristics table 7 provides the clock input (clkin/pci_sync_i n) dc timing specifications for the mpc8323e. local bus i/o load = 25 pf 1 pair of clocks 66 mhz, 32 bits ? ? 0.12 w ? pci i/o load = 30 pf 66 mhz, 32 bits ? ? 0.057 w ? quicc engine block and other i/os utopia 8-bit 31 phys ? ? 0.041 w multiply by number of interfaces used. tdm serial ? ? 0.001 w tdm nibble ? ? 0.004 w hdlc/tran serial ? ? 0.003 w hdlc/tran nibble ? ? 0.025 w duart ? ? 0.017 w miis ? ? 0.009 w rmii ? ? 0.009 w ethernet management ? ? 0.002 w usb ? ? 0.001 w spi ? ? 0.001 w timer output ? ? 0.002 w table 7. clkin dc electrical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.7 ov dd +0.3 v input low voltage ? v il ?0.3 0.4 v table 6. estimated typical i/o power dissipation (continued)
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 11 reset initialization 4.2 ac electrical characteristics the primary clock source for the mpc8323e can be one of two inputs, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. table 8 provides the clock input (clkin/pci_clk) ac timing specifications for the mpc8323e. 5 reset initialization this section describes the ac electrical specifications for the reset initialization timing requirements of the mpc8323e. table 9 provides the reset initialization ac timing specifications for the reset component(s). clkin input current 0 v v in ov dd i in ?5 a pci_sync_in input current 0 v v in 0.5 v or ov dd ? 0.5 v v in ov dd i in ?5 a pci_sync_in input current 0.5 v v in ov dd ? 0.5 v i in ?50 a table 8. clkin ac timing specifications parameter/condition symbol min typical max unit notes clkin/pci_clk frequency f clkin 25 ? 66.67 mhz 1 clkin/pci_clk cycle time t clkin 15 ? ? ns ? clkin rise and fall time t kh , t kl 0.6 0.8 4 ns 2 pci_clk rise and fall time t pch , t pcl 0.6 0.8 1.2 ns 2 clkin/pci_clk duty cycle t khk /t clkin 40 ? 60 % 3 clkin/pci_clk jitter ? ? ? 150 ps 4, 5 notes: 1. caution: the system, core, security, and quicc engine block must not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for clkin/pci_clk are measured at 0.4 and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the clkin/pci_clk driver?s closed loop jitter bandwidth should be < 500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track clkin drivers with the specified jitter. table 9. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset or sreset (input) to activate reset flow 32 ? t pci_sync_in 1 required assertion time of poreset with stable clock applied to clkin when the mpc8323e is in pci host mode 32 ? t clkin 2 required assertion time of poreset with stable clock applied to pci_sync_in when the mpc8323e is in pci agent mode 32 ? t pci_sync_in 1 table 7. clkin dc electrical characteristics (continued)
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 12 freescale semiconductor reset initialization table 10 provides the pll lock times. 5.1 reset signals dc electrical characteristics table 11 provides the dc electrical characteristics for the mpc8323e reset signals mentioned in table 9 . hreset /sreset assertion (output) 512 ? t pci_sync_in 1 hreset negation to sreset negation (output) 16 ? t pci_sync_in 1 input setup time for por configuration signals (cfg_reset_source[0:2] and cfg_clkin_div ) with respect to negation of poreset when the mpc8323e is in pci host mode 4?t clkin 2 input setup time for por configuration signals (cfg_reset_source[0:2] and cfg_clkin_div ) with respect to negation of poreset when the mpc8323e is in pci agent mode 4?t pci_sync_in 1 input hold time for por config signals with respect to negation of hreset 0? ns ? time for the mpc8323e to turn off por configuration signals with respect to the assertion of hreset ?4 ns 3 time for the mpc8323e to turn on por configuration signals with respect to the negation of hreset 1?t pci_sync_in 1, 3 notes: 1. t pci_sync_in is the clock period of the input clock applied to pci_sync_in. when the mpc8323e is in pci host mode the primary clock is applied to the clkin input, and pci_sync_in period depends on the value of cfg_clkin_div . see the mpc8323e powerquicc ii pro integrated communications processor reference manual for more details. 2. t clkin is the clock period of the input clock applied to clkin. it is only valid when the mpc8323e is in pci host mode. see the mpc8323e powerquicc ii pro integrated communications processor reference manual for more details. 3. por configuration signals consists of cfg_reset_source[0:2] and cfg_clkin_div . table 10. pll lock times parameter/condition min max unit notes pll lock times ? 100 s? table 11. reset signals dc electrical characteristics characteristic symbol condition min max unit notes output high voltage v oh i oh = ?6.0 ma 2.4 ? v 1 output low voltage v ol i ol = 6.0 ma ? 0.5 v 1 output low voltage v ol i ol = 3.2 ma ? 0.4 v 1 input high voltage v ih ?2.0ov dd +0.3 v 1 input low voltage v il ? ?0.3 0.8 v ? table 9. reset initialization timing specifications (continued) parameter/condition min max unit notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 13 ddr1 and ddr2 sdram 6 ddr1 and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr1 and ddr2 sdram interface of the mpc8323e. note that ddr1 sdram is d n _gv dd (typ) = 2.5 v and ddr2 sdram is d n _gv dd (typ) = 1.8 v. the ac electrical specifications are the same for ddr1 and ddr2 sdram. 6.1 ddr1 and ddr2 sdram dc electrical characteristics table 12 provides the recommended operating conditions for the ddr2 sdram component(s) of the mpc8323e when d n _gv dd (typ) = 1.8 v . table 13 provides the ddr2 capacitance when d n _gv dd (typ) = 1.8 v. input current i in 0 v v in ov dd ? 5 a? note: 1. this specification applies when operating from 3.3 v supply. table 12. ddr2 sdram dc electrical characteristics for d n _ gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes i/o supply voltage d n _ gv dd 1.71 1.89 v 1 i/o reference voltage mvref n ref 0.49 d n _ gv dd 0.51 d n _ gv dd v2 i/o termination voltage v tt mvref n ref ? 0.04 mvref n ref +0.04 v 3 input high voltage v ih mvref n ref + 0.125 d n _ gv dd +0.3 v ? input low voltage v il ?0.3 mvref n ref ? 0.125 v ? output leakage current i oz ?9.9 9.9 a4 output high current (v out = 1.35 v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma ? notes: 1. d n _ gv dd is expected to be within 50 mv of the dram d n _ gv dd at all times. 2. mvref n ref is expected to be equal to 0.5 d n _ gv dd , and to track d n _ gv dd dc variations as measured at the receiver. peak-to-peak noise on mvref n ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mvref n ref . this rail should track variations in the dc level of mvref n ref . 4. output leakage is measured with all outputs disabled, 0 v v out d n _ gv dd . table 13. ddr2 sdram capacitance for d n _ gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 table 11. reset signals dc electrical characteristics (continued) characteristic symbol condition min max unit notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 14 freescale semiconductor ddr1 and ddr2 sdram table 14 provides the recommended operating conditions for the ddr1 sdram component(s) of the mpc8323e when d n _gv dd (typ) = 2.5 v. table 15 provides the ddr1 capacitance d n _gv dd (typ) = 2.5 v. delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. d n _ gv dd = 1.8 v 0.090 v, f = 1 mhz, t a =25c, v out = d n _ gv dd 2, v out (peak-to-peak) = 0.2 v. table 14. ddr1 sdram dc electrical characteristics for d n _ gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes i/o supply voltage d n _ gv dd 2.375 2.625 v 1 i/o reference voltage mvref n ref 0.49 d n _ gv dd 0.51 d n _ gv dd v2 i/o termination voltage v tt mvref n ref ? 0.04 mvref n ref + 0.04 v 3 input high voltage v ih mvref n ref + 0.15 d n _ gv dd + 0.3 v ? input low voltage v il ?0.3 mvref n ref ? 0.15 v ? output leakage current i oz ?9.9 ?9.9 a4 output high current (v out = 1.95 v) i oh ?16.2 ? ma ? output low current (v out = 0.35 v) i ol 16.2 ? ma ? notes: 1. d n _ gv dd is expected to be within 50 mv of the dram d n _ gv dd at all times. 2. mvref n ref is expected to be equal to 0.5 d n _ gv dd , and to track d n _ gv dd dc variations as measured at the receiver. peak-to-peak noise on mvref n ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mvref n ref . this rail should track variations in the dc level of mvref n ref . 4. output leakage is measured with all outputs disabled, 0 v v out d n _ gv dd . table 15. ddr1 sdram capacitance for d n _ gv dd (typ) = 2.5 v interface parameter/condition symbol min max unit notes input/output capacitance: dq,dqs c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. d n _ gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25 c, v out = d n _ gv dd 2, v out (peak-to-peak) = 0.2 v. table 13. ddr2 sdram capacitance for d n _ gv dd (typ) = 1.8 v
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 15 ddr1 and ddr2 sdram 6.2 ddr1 and ddr2 sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr1 and ddr2 sdram interface. 6.2.1 ddr1 and ddr2 sdram input ac timing specifications table 16 provides the input ac timing specifications for the ddr2 sdram (d n _gv dd (typ) = 1.8 v). table 17 provides the input ac timing specifications for the ddr1 sdram (d n _gv dd (typ) = 2.5 v). table 18 provides the input ac timing specifications for the ddr1 and ddr2 sdram interface. table 16. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions with d n _gv dd of 1.8 5%. parameter symbol min max unit notes ac input low voltage v il ? mvref n ref ? 0.25 v ? ac input high voltage v ih mvref n ref + 0.25 ? v ? table 17. ddr1 sdram input ac timing specifications for 2.5 v interface at recommended operating conditions with d n _gv dd of 2.5 5%. parameter symbol min max unit notes ac input low voltage v il ? mvref n ref ? 0.31 v ? ac input high voltage v ih mvref n ref + 0.31 ? v ? table 18. ddr1 and ddr2 sdram input ac timing specifications at recommended operating conditions with d n _gv dd of (1.8 or 2.5 v) 5%. parameter symbol min max unit notes controller skew for mdqs?mdq/mdm t ciskew ps 1, 2 266 mhz 200 mhz ?750 ?1250 750 1250 notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that is captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the following equation: t diskew = (t/4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew .
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 16 freescale semiconductor ddr1 and ddr2 sdram figure 4 shows the input timing diagram for the ddr controller. figure 4. ddr input timing diagram 6.2.2 ddr1 and ddr2 sdram output ac timing specifications table 19 provides the output ac timing specifications for the ddr1 and ddr2 sdram interfaces. table 19. ddr1 and ddr2 sdram output ac timing specifications at recommended operating conditions with d n _gv dd of (1.8 or 2.5 v) 5%. parameter symbol 1 min max unit notes mck cycle time, (mck/mck crossing) t mck 7.5 10 ns 2 addr/cmd output setup with respect to mck t ddkhas ns 3 266 mhz 200 mhz 2.5 3.5 ? ? addr/cmd output hold with respect to mck t ddkhax ns 3 266 mhz 200 mhz 2.5 3.5 ? ? mcs output setup with respect to mck t ddkhcs ns 3 266 mhz 200 mhz 2.5 3.5 ? ? mcs output hold with respect to mck t ddkhcx ns 3 266 mhz 200 mhz 2.5 3.5 ? ? mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mck [n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 17 ddr1 and ddr2 sdram mdq/mdm output setup with respect to mdqs t ddkhds, t ddklds ns 5 266 mhz 200 mhz 0.9 1.0 ? ? mdq/mdm output hold with respect to mdqs t ddkhdx, t ddkldx ps 5 266 mhz 200 mhz 1100 1200 ? ? mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck +0.6 ns 6 mdqs epilogue end t ddkhme ?0.6 0.6 ns 6 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mdm/mdqs. for the addr/cmd setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. this is typically set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the mpc8323e powerquicc ii pro integrated communications processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck(n) at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. table 19. ddr1 and ddr2 sdram output ac timing specifications (continued) at recommended operating conditions with d n _gv dd of (1.8 or 2.5 v) 5%. parameter symbol 1 min max unit notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 18 freescale semiconductor ddr1 and ddr2 sdram figure 5 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 5. timing diagram for t ddkhmh figure 6 shows the ddr1 and ddr2 sdram output timing diagram. figure 6. ddr1 and ddr2 sdram output timing diagram mdqs mck mck t mck mdqs t ddkhmh (max) = 0.6 ns t ddkhmh (min) = ?0.6 ns addr/cmd t ddkhas ,t ddkhcs t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhme t ddkhmp t ddkhmh
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 19 duart 7duart this section describes the dc and ac electri cal specifications for the duart interface of the mpc8323e. 7.1 duart dc electrical characteristics table 20 provides the dc electrical characteristic s for the duart interface of the mpc8323e. 7.2 duart ac electrical specifications table 21 provides the ac timing parameters for the duart interface of the mpc8323e. 8 ethernet and mii management this section provides the ac and dc electrical ch aracteristics for ethernet and mii management. 8.1 ethernet controller (10/100 mbps)?mii/rmii electrical characteristics the electrical characteristics specified here apply to all mii (media independent interface) and rmii (reduced media independent interface), except mdio (management data input/output) and mdc table 20. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage ov dd v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v input current (0 v v in ov dd ) 1 i in ?5 a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 21. duart ac timing specifications parameter value unit notes minimum baud rate 256 baud maximum baud rate > 1,000,000 baud 1 oversample rate 16 ? 2 notes: 1. actual attainable baud rate is limited by the latency of interrupt processing. 2. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 20 freescale semiconductor ethernet and mii management (management data clock). the mii and rmii are defined for 3.3 v. the electrical characteristics for mdio and mdc are specified in section 8.3, ?ethernet management interface electrical characteristics . ? 8.1.1 dc electrical characteristics all mii and rmii drivers and receivers comply with the dc parametric attributes specified in table 22 . 8.2 mii and rmii ac timing specifications the ac timing specifications for mii and rmii are presented in this section. 8.2.1 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 8.2.1.1 mii transmit ac timing specifications table 23 provides the mii transmit ac timing specifications. table 22. mii and rmii dc electrical characteristics parameter symbol conditions min max unit supply voltage 3.3 v ov dd ? 2.97 3.63 v output high voltage v oh i oh = ?4.0 ma ov dd = min 2.40 ov dd + 0.3 v output low voltage v ol i ol = 4.0 ma ov dd = min gnd 0.50 v input high voltage v ih ??2.0ov dd + 0.3 v input low voltage v il ? ? ?0.3 0.90 v input current i in 0 v v in ov dd ?5 a table 23. mii transmit ac timing specifications at recommended operating conditions with ov dd of 3.3 v 10%. parameter/condition symbol 1 min typical max unit tx_clk clock period 10 mbps t mtx ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh /t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise time t mtxr 1.0 ? 4.0 ns
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 21 ethernet and mii management figure 7 shows the mii transmit ac timing diagram. figure 7. mii transmit ac timing diagram 8.2.1.2 mii receive ac timing specifications table 24 provides the mii receive ac timing specifications. tx_clk data clock fall time t mtxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 24. mii receive ac timing specifications at recommended operating conditions with ov dd of 3.3 v 10%. parameter/condition symbol 1 min typical max unit rx_clk clock period 10 mbps t mrx ?400?ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise time t mrxr 1.0 ? 4.0 ns table 23. mii transmit ac timing specifications (continued) at recommended operating conditions with ov dd of 3.3 v 10%. parameter/condition symbol 1 min typical max unit tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 22 freescale semiconductor ethernet and mii management figure 8 provides the ac test load. figure 8. ac test load figure 9 shows the mii receive ac timing diagram. figure 9. mii receive ac timing diagram 8.2.2 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. rx_clk clock fall time t mrxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 24. mii receive ac timing specifications (continued) at recommended operating conditions with ov dd of 3.3 v 10%. parameter/condition symbol 1 min typical max unit output z 0 = 50 ov dd /2 r l = 50 rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 23 ethernet and mii management 8.2.2.1 rmii transmit ac timing specifications table 23 provides the rmii transmit ac timing specifications. figure 10 shows the rmii transmit ac timing diagram. figure 10. rmii transmit ac timing diagram 8.2.2.2 rmii receive ac timing specifications table 24 provides the rmii receive ac timing specifications. table 25. rmii transmit ac timing specifications at recommended operating conditions with ov dd of 3.3 v 10%. parameter/condition symbol 1 min typical max unit ref_clk clock t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % ref_clk to rmii data txd[1:0], tx_en delay t rmtkhdx 2 ? 10 ns ref_clk data clock rise v il (min) to v ih (max) t rmxr 1.0 ? 4.0 ns ref_clk data clock fall v ih (max) to v il (min) t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t rmtkhdx symbolizes rmii transmit timing (rmt) for the time t rmx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t rmx represents the rmii(rm) reference (x) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 26. rmii receive ac timing specifications at recommended operating conditions with ov dd of 3.3 v 10%. parameter/condition symbol 1 min typical max unit ref_clk clock period t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % rxd[1:0], crs_dv, rx_er setup time to ref_clk t rmrdvkh 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk t rmrdxkh 2.0 ? ? ns ref_clk clock rise v il (min) to v ih (max) t rmxr 1.0 ? 4.0 ns ref_clk txd[1:0] t rmtkhdx t rmx t rmxh t rmxr t rmxf tx_en
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 24 freescale semiconductor ethernet and mii management figure 11 provides the ac test load. figure 11. ac test load figure 12 shows the rmii receive ac timing diagram. figure 12. rmii receive ac timing diagram 8.3 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). the electrical characteristics for mii, and rmii are specified in section 8.1, ?ethernet controller (10/100 mbps)?mii/rmii electrical characteristics.? ref_clk clock fall time v ih (max) to v il (min) t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t rmrdvkh symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) reach the valid state (v) relative to the t rmx clock reference (k) going to the high (h) state or setup time. also, t rmrdxkl symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) went invalid (x) relative to the t rmx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particul ar functional. for example, the subscript of t rmx represents the rmii (rm) reference (x) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 26. rmii receive ac timing specifications (continued) at recommended operating conditions with ov dd of 3.3 v 10%. parameter/condition symbol 1 min typical max unit output z 0 = 50 ov dd /2 r l = 50 ref_clk rxd[1:0] t rmrdxkh t rmx t rmxh t rmxr t rmxf crs_dv rx_er t rmrdvkh valid data
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 25 ethernet and mii management 8.3.1 mii management dc electrical characteristics mdc and mdio are defined to operate at a supply voltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 27 . 8.3.2 mii management ac electrical specifications table 28 provides the mii management ac timing specifications. table 27. mii management dc electrical characteristics when powered at 3.3 v parameter symbol conditions min max unit supply voltage (3.3 v) ov dd ? 2.97 3.63 v output high voltage v oh i oh = ?1.0 ma ov dd = min 2.10 ov dd + 0.3 v output low voltage v ol i ol = 1.0 ma ov dd = min gnd 0.50 v input high voltage v ih ?2.00?v input low voltage v il ??0.80v input current i in 0 v v in ov dd ?5 a table 28. mii management ac timing specifications at recommended operating conditions with ov dd is 3.3 v 10%. parameter/condition symbol 1 min typical max unit notes mdc frequency f mdc ?2.5?mhz? mdc period t mdc ?400?ns? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio delay t mdkhdx 10 ? 70 ns ? mdio to mdc setup time t mddvkh 5??ns? mdio to mdc hold time t mddxkh 0??ns? mdc rise time t mdcr ? ? 10 ns ? mdc fall time t mdhf ? ? 10 ns ? note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall).
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 26 freescale semiconductor local bus figure 13 shows the mii management ac timing diagram. figure 13. mii management interface timing diagram 9 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8323e. 9.1 local bus dc electrical characteristics table 29 provides the dc electrical characteristics for the local bus interface. 9.2 local bus ac electrical specifications table 30 describes the general timi ng parameters of the local bus interface of the mpc8323e. table 29. local bus dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v input current i in ?5 a table 30. local bus general timing parameters parameter symbol 1 min max unit notes local bus cycle time t lbk 15 ? ns 2 input setup to local bus clock (lclk n )t lbivkh 7?ns3, 4 input hold from local bus clock (lclk n )t lbixkh 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 27 local bus figure 14 provides the ac test load for the local bus. figure 14. local bus c test load lale output fall to lad output transition (latch hold time) t lbotot2 3?ns6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock (lclk n ) to output valid t lbkhov ?3ns3 local bus clock (lclk n ) to output high impedance for lad/ldp t lbkhoz ?4ns8 local bus clock (lclk n ) duty cycle t lbdc 47 53 % ? local bus clock (lclk n ) jitter specification t lbrj ? 400 ps ? delay between the input clock (pci_sync_in) of local bus output clock (lclk n ) t lbcdl ?1.7ns? notes : 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). 2. all timings are in reference to falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or rising edge of lclk0 (for all other inputs). 3. all signals are measured from ov dd /2 of the rising/falling edge of lclk0 to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is not set and the load on lale output pin is at least 10 pf less than the load on lad output pins. 6. t lbotot2 should be used when rcwh[lale] is set and the load on lale output pin is at least 10 pf less than the load on lad output pins. 7. t lbotot3 should be used when rcwh[lale] is set and the load on lale output pin equals to the load on lad output pins. 8. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. table 30. local bus general timing parameters (continued) parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 28 freescale semiconductor local bus figure 15 through figure 17 show the local bus signals. figure 15. local bus signals, nonspecial signals only figure 16. local bus sign als, gpcm/upm signals for lcrr[clkdiv] = 2 output signals: lbctl/lbcke/loe t lbkhov t lbkhov lclk[n] input signals: lad[0:15] output signals: lad[0:15] t lbixkh t lbivkh t lbkhoz t lbotot lale input signal: lgta t lbixkh t lbivkh t lbixkh lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 input signals: lad[0:15]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:1]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 29 jtag figure 17. local bus sign als, gpcm/upm signals for lcrr[clkdiv] = 4 10 jtag this section describes the dc and ac electrical specifications for the ieee std. 1149.1? (jtag) interface of the mpc8323e. 10.1 jtag dc electrical characteristics table 31 provides the dc electrical characteristics for the ieee std. 1149.1 (jtag) interface of the mpc8323e. table 31. jtag interface dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.5ov dd +0.3 v lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 upm mode output signals: lcs [0:3]/lbs [0:1]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz t2 t4 input signals: lad[0:15]
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 30 freescale semiconductor jtag 10.2 jtag ac electrical characteristics this section describes the ac electrical specificati ons for the ieee std. 1149.1 (jtag) interface of the mpc8323e. table 32 provides the jtag ac timing specifications as defined in figure 19 through figure 22 . input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?5 a table 32. jtag ac timing specifications (independent of clkin) 1 at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz ? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 11 ? ns ? jtag external clock rise and fall times t jtgr , t jtgf 02ns? trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 15 15 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns 5 table 31. jtag interface dc electrical characteristics (continued) characteristic symbol condition min max unit
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 31 jtag figure 18 provides the ac test load for tdo and the boundary-scan outputs of the mpc8323e. figure 18. ac test load for the jtag interface figure 19 provides the jtag clock input timing diagram. figure 19. jtag clock input timing diagram figure 20 provides the trst timing diagram. figure 20. trst timing diagram jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5, 6 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 14 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design and characterization. table 32. jtag ac timing specifications (independent of clkin) 1 (continued) at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 32 freescale semiconductor jtag figure 21 provides the boundary-scan timing diagram. figure 21. boundary-scan timing diagram figure 22 provides the test access port timing diagram. figure 22. test access port timing diagram vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 33 i 2 c 11 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the mpc8323e. 11.1 i 2 c dc electrical characteristics table 33 provides the dc electrical characteristics for the i 2 c interface of the mpc8323e. 11.2 i 2 c ac electrical specifications table 34 provides the ac timing parameters for the i 2 c interface of the mpc8323e. table 33. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 10%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.4v1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns3 capacitance for each i/o pin c i ?10pf? input current (0 v v in ov dd )i in ?5 a4 notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. refer to the mpc8323e powerquicc ii pro integrated communications processor reference manual for information on the digital filter used. 4. i/o pins obstructs the sda and scl lines if ov dd is switched off. table 34. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta b l e 3 3 ). parameter symbol 1 min max unit scl clock frequency f i2c 0400khz low period of the scl clock t i2cl 1.3 ? s high period of the scl clock t i2ch 0.6 ? s setup time for a repeated start condition t i2svkh 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s data setup time t i2dvkh 100 ? ns data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 s
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 34 freescale semiconductor i 2 c figure 23 provides the ac test load for the i 2 c. figure 23. i 2 c ac test load figure 24 shows the ac timing diagram for the i 2 c bus. figure 24. i 2 c bus ac timing diagram rise time of both sda and scl signals t i2cr 20 + 0.1 c b 4 300 ns fall time of both sda and scl signals t i2cf 20 + 0.1 c b 4 300 ns setup time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. mpc8323e provides a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. table 34. i 2 c ac electrical specifications (continued) all values refer to v ih (min) and v il (max) levels (see ta b l e 3 3 ). parameter symbol 1 min max unit output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 35 pci 12 pci this section describes the dc and ac electrical specifications for the pci bus of the mpc8323e. 12.1 pci dc electrical characteristics table 35 provides the dc electrical characteristics for the pci interface of the mpc8323e. 12.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus of the mpc8323e. note that the pci_clk or pci_sync_in signal is used as the pci input clock depending on whether the mpc8323e is configured as a host or agent device. table 36 shows the pci ac timing specifications at 66 mhz. . table 35. pci dc electrical characteristics 1,2 parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 2 ov dd + 0.3 v low-level input voltage v il v out v ol (max) ?0.3 0.8 v high-level output voltage v oh ov dd = min, i oh = ?100 a ov dd ? 0.2 ? v low-level output voltage v ol ov dd = min, i ol = 100 a ?0.2v input current i in 0 v v in ov dd ? 5 a notes: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . 2. ranges listed do not meet the full range of the dc specifications of the pci 2.3 local bus specifications. table 36. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?6.0ns2 output hold from clock t pckhox 1?ns2 clock to output high impedence t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0?ns2, 4 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.3 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 36 freescale semiconductor pci table 37 shows the pci ac timing specifications at 33 mhz. figure 25 provides the ac test load for pci. figure 25. pci ac test load figure 26 shows the pci input ac timing conditions. figure 26. pci input ac timing measurement conditions table 37. pci ac timing specifications at 33 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?11ns2 output hold from clock t pckhox 2?ns2 clock to output high impedence t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0?ns2, 4 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.3 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. output z 0 = 50 ov dd /2 r l = 50
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 37 timers figure 27 shows the pci output ac timing conditions. figure 27. pci output ac timing measurement condition 13 timers this section describes the dc and ac electrical specifications for the timers of the mpc8323e. 13.1 timer dc electrical characteristics table 38 provides the dc electrical characteristics for the mpc8323e timer pins, including tin, tout , tgate , and rtc_clk. 13.2 timer ac timing specifications table 39 provides the timer input and output ac timing specifications. table 38. timer dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ? 5 a table 39. timer input ac timing specifications 1 characteristic symbol 2 min unit timers inputs?minimum pulse width t tiwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. timer inputs and outputs are asynchronous to any visible clock. timer outputs should be synchronized before use by any external synchronous logic. timer inputs are required to be valid for at least t tiwid ns to ensure proper operation. clk output delay t pckhov high-impedance t pckhoz output t pckhox
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 38 freescale semiconductor gpio figure 28 provides the ac test load for the timers. figure 28. timers ac test load 14 gpio this section describes the dc and ac electrical specifications for the gpio of the mpc8323e. 14.1 gpio dc electrical characteristics table 11 provides the dc electrical characteristics for the mpc8323e gpio. 14.2 gpio ac timing specifications table 41 provides the gpio input and output ac timing specifications. table 40. gpio dc electrical characteristics characteristic symbol condition min max unit notes output high voltage v oh i oh = ?6.0 ma 2.4 ? v 1 output low voltage v ol i ol = 6.0 ma ? 0.5 v 1 output low voltage v ol i ol = 3.2 ma ? 0.4 v 1 input high voltage v ih ?2.0ov dd +0.3 v 1 input low voltage v il ? ?0.3 0.8 v ? input current i in 0 v v in ov dd ? 5 a? note: 1. this specification applies when operating from 3.3-v supply. table 41. gpio input ac timing specifications 1 characteristic symbol 2 min unit gpio inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to any visible clock. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. output z 0 = 50 ov dd /2 r l = 50
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 39 ipic figure 29 provides the ac test load for the gpio. figure 29. gpio ac test load 15 ipic this section describes the dc and ac electrical speci fications for the external interrupt pins of the mpc8323e. 15.1 ipic dc electrical characteristics table 42 provides the dc electrical characteristics for the external interrupt pins of the mpc8323e. 15.2 ipic ac timing specifications table 43 provides the ipic input and output ac timing specifications. table 42. ipic dc electrical characteristics 1,2 characteristic symbol condition min max unit input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ? ?0.3 0.8 v input current i in ??5 a output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applies for pins irq [0:7], irq_out , mcp_out , and ce ports interrupts. 2. irq_out and mcp_out are open drain pins, thus v oh is not relevant for those pins. table 43. ipic input ac timing specifications 1 characteristic symbol 2 min unit ipic inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. ipic inputs and outputs are asynchronous to any visible clock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inputs are required to be valid for at least t piwid ns to ensure proper operation when working in edge triggered mode. output z 0 = 50 ov dd /2 r l = 50
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 40 freescale semiconductor spi 16 spi this section describes the dc and ac electrical specifications for the spi of the mpc8323e. 16.1 spi dc electrical characteristics table 44 provides the dc electrical characteristics for the mpc8323e spi. 16.2 spi ac timing specifications table 45 and provide the spi input and output ac timing specifications. figure 30 provides the ac test load for the spi. figure 30. spi ac test load table 44. spi dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ? 5 a table 45. spi ac timing specifications 1 characteristic symbol 2 min max unit spi outputs?master mode (internal clock) delay t nikhov 0.5 6 ns spi outputs?slave mode (external clock) delay t nekhov 28ns spi inputs?master mode (internal clock) input setup time t niivkh 6?ns spi inputs?master mode (internal clock) input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns spi inputs?slave mode (external clock) input hold time t neixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhov symbolizes the nmsi outputs internal timing (ni) for the time t spi memory clock reference (k) goes from the high state (h) until outputs (o) are valid (v). output z 0 = 50 ov dd /2 r l = 50
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 41 tdm/si figure 31 and figure 32 represent the ac timing from table 45 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 31 shows the spi timing in slave mode (external clock). figure 31. spi ac timing in slave mode (external clock) diagram figure 32 shows the spi timing in master mode (internal clock). figure 32. spi ac timing in master mode (internal clock) diagram 17 tdm/si this section describes the dc and ac electrical specifications for the time-division-multiplexed and serial interface of the mpc8323e. 17.1 tdm/si dc electrical characteristics table 46 provides the dc electrical characteristics for the mpc8323e tdm/si. table 46. tdm/si dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v spiclk (input) t neixkh t neivkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 42 freescale semiconductor tdm/si 17.2 tdm/si ac timing specifications table 47 provides the tdm/si input and output ac timing specifications. figure 33 provides the ac test load for the tdm/si. figure 33. tdm/si ac test load figure 34 represents the ac timing from table 47 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 34. tdm/si ac timing (external clock) diagram input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ?5 a table 47. tdm/si ac timing specifications 1 characteristic symbol 2 min max unit tdm/si outputs?external clock delay t sekhov 212ns tdm/si outputs?external clock high impedance t sekhox 210ns tdm/si inputs?external clock input setup time t seivkh 5?ns tdm/si inputs?external clock input hold time t seixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t sekhox symbolizes the tdm/si outputs external timing (se) for the time t tdm/si memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 46. tdm/si dc electrical characteristics (continued) characteristic symbol condition min max unit output z 0 = 50 ov dd /2 r l = 50 tdm/siclk (input) t seixkh t seivkh t sekhov input signals: tdm/si (see note) output signals: tdm/si (see note) note: the clock edge is selectable on tdm/si. t sekhox
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 43 utopia 18 utopia this section describes the utopia dc and ac electrical specifications of the mpc8323e. note the mpc8321e and mpc8321 do not support utopia. 18.1 utopia dc electrical characteristics table 48 provides the dc electrical char acteristics for the mpc8323e utopia. 18.2 utopia ac timing specifications table 49 provides the utopia input and output ac timing specifications. table 48. utopia dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ? 5 a table 49. utopia ac timing specifications 1 characteristic symbol 2 min max unit utopia outputs?internal clock delay t uikhov 05.5ns utopia outputs?external clock delay t uekhov 18ns utopia outputs?internal clock high impedance t uikhox 05.5ns utopia outputs?external clock high impedance t uekhox 18ns utopia inputs?internal clock input setup time t uiivkh 8?ns utopia inputs?external clock input setup time t ueivkh 4?ns utopia inputs?internal clock input hold time t uiixkh 0?ns utopia inputs?external clock input hold time t ueixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t uikhox symbolizes the utopia outputs internal timing (ui) for the time t utopia memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x).
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 44 freescale semiconductor utopia figure 35 provides the ac test load for the utopia. figure 35. utopia ac test load figure 36 and figure 37 represent the ac timing from table 49 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 36 shows the utopia timing with external clock. figure 36. utopia ac timing (external clock) diagram figure 37 shows the utopia timing with internal clock. figure 37. utopia ac timing (internal clock) diagram output z 0 = 50 ov dd /2 r l = 50 utopiaclk (input) t ueixkh t ueivkh t uekhov input signals: utopia output signals: utopia t uekhox utopiaclk (output) t uiixkh t uikhov input signals: utopia output signals: utopia t uiivkh t uikhox
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 45 hdlc, bisync, transparent, and synchronous uart 19 hdlc, bisync, transparent, and synchronous uart this section describes the dc and ac electrical speci fications for the high level data link control (hdlc), bisync, transparent, and synchronous uart of the mpc8323e. 19.1 hdlc, bisync, transparent, and synchronous uart dc electrical characteristics table 50 provides the dc electrical characteristics fo r the mpc8323e hdlc, bisync, transparent, and synchronous uart protocols. 19.2 hdlc, bisync, transparent, and synchronous uart ac timing specifications table 51 provides the input and output ac timing specifi cations for hdlc, bisync, and transparent uart protocols. table 50. hdlc, bisync, transparent, and synchronous uart dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ? ?0.3 0.8 v input current i in 0 v v in ov dd ? 5 a table 51. hdlc, bisync, and transparent uart ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t hikhov 05.5ns outputs?external clock delay t hekhov 110ns outputs?internal clock high impedance t hikhox 05.5ns outputs?external clock high impedance t hekhox 18ns inputs?internal clock input setup time t hiivkh 6?ns inputs?external clock input setup time t heivkh 4?ns inputs?internal clock input hold time t hiixkh 0?ns
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 46 freescale semiconductor hdlc, bisync, transparent, and synchronous uart figure 38 provides the ac test load. figure 38. ac test load figure 39 and figure 40 represent the ac timing from table 51 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. inputs?external clock input hold time t heixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 52. synchronous uart ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t uaikhov 05.5ns outputs?external clock delay t uaekhov 110ns outputs?internal clock high impedance t uaikhox 05.5ns outputs?external clock high impedance t uaekhox 18ns inputs?internal clock input setup time t uaiivkh 6?ns inputs?external clock input setup time t uaeivkh 4?ns inputs?internal clock input hold time t uaiixkh 0?ns inputs?external clock input hold time t uaeixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t uaikhox symbolizes the outputs internal timing (uai) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 51. hdlc, bisync, and transparent uart ac timing specifications 1 (continued) characteristic symbol 2 min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 47 hdlc, bisync, transparent, and synchronous uart figure 39 shows the timing with external clock. figure 39. ac timing (external clock) diagram figure 40 shows the timing with internal clock. figure 40. ac timing (internal clock) diagram serial clk (input) t heixkh t heivkh t hekhov input signals: (see note) output signals: (see note) note: the clock edge is selectable. t hekhox serial clk (output) t hiixkh t hikhov input signals: (see note) output signals: (see note) t hiivkh t hikhox note: the clock edge is selectable.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 48 freescale semiconductor usb 20 usb this section provides the ac and dc electrical sp ecifications for the usb interface of the mpc8323e. 20.1 usb dc electrical characteristics table 53 provides the dc electrical characteristics for the usb interface. 20.2 usb ac electrical specifications table 54 describes the general timi ng parameters of the usb interface of the mpc8323e. figure 41 provide the ac test load for the usb. figure 41. usb ac test load table 53. usb dc electrical characteristics 1 parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v input current i in ?5 a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta ble 2 . table 54. usb general timing parameters parameter symbol 1 min max unit notes usb clock cycle time t usck 20.83 ? ns full speed 48 mhz usb clock cycle time t usck 166.67 ? ns low speed 6 mhz skew between txp and txn t ustspn ?5ns ? skew among rxp, rxn, and rxd t usrspnd ? 10 ns full speed transitions skew among rxp, rxn, and rxd t usrpnd ? 100 ns low speed transitions notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(state)(signal) for receive signals and t (first two letters of functional block)(state)(signal) for transmit signals. for example, t usrspnd symbolizes usb timing (us) for the usb receive signals skew (rs) among rxp, rxn, and rxd (pnd). also, t ustspn symbolizes usb timing (us) for the usb transmit signals skew (ts) between txp and txn (pn). 2. skew measurements are done at ov dd /2 of the rising or falling edge of the signals. output z 0 = 50 ov dd /2 r l = 50
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 49 package and pin listings 21 package and pin listings this section details package parameters, pin assignm ents, and dimensions. the mpc8323e is available in a thermally enhanced plastic ball grid array (pbga); see section 21.1, ?package parameters for the mpc8323e pbga,? and section 21.2, ?mechanical dimensions of the mpc8323e pbga,? for information on the pbga. 21.1 package parameters for the mpc8323e pbga the package parameters are as provided in the following list. the package type is 27 mm 27 mm, 516 pbga. package outline 27 mm 27 mm interconnects 516 pitch 1.00 mm module height (typical) 2.25 mm solder balls 62 sn/36 pb/2 ag (zq package) 95.5 sn/0.5 cu/4ag (vr package) ball diameter (typical) 0.6 mm 21.2 mechanical dimensions of the mpc8323e pbga figure 42 shows the mechanical dimensions and bottom surface nomenclature of the mpc8323e, 516-pbga package.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 50 freescale semiconductor package and pin listings notes: 1.all dimensions are in millimeters. 2.dimensions and tolerances per asme y14.5m-1994. 3.maximum solder ball diameter measured parallel to datum a. 4.datum a, the seating plane, is determined by the spherical crowns of the solder balls. figure 42. mechanical dimensions and bottom surface nomenclature of the mpc8323e pbga
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 51 package and pin listings 21.3 pinout listings table 55 shows the pin list of the mpc8323e. table 55. mpc8323e pbga pinout listing signal package pin number pin type power supply notes ddr memory controller interface memc_mdq0 ae9 io gv dd ? memc_mdq1 ad10 io gv dd ? memc_mdq2 af10 io gv dd ? memc_mdq3 af9 io gv dd ? memc_mdq4 af7 io gv dd ? memc_mdq5 ae10 io gv dd ? memc_mdq6 ad9 io gv dd ? memc_mdq7 af8 io gv dd ? memc_mdq8 ae6 io gv dd ? memc_mdq9 ad7 io gv dd ? memc_mdq10 af6 io gv dd ? memc_mdq11 ac7 io gv dd ? memc_mdq12 ad8 io gv dd ? memc_mdq13 ae7 io gv dd ? memc_mdq14 ad6 io gv dd ? memc_mdq15 af5 io gv dd ? memc_mdq16 ad18 io gv dd ? memc_mdq17 ae19 io gv dd ? memc_mdq18 af17 io gv dd ? memc_mdq19 af19 io gv dd ? memc_mdq20 af18 io gv dd ? memc_mdq21 ae18 io gv dd ? memc_mdq22 af20 io gv dd ? memc_mdq23 ad19 io gv dd ? memc_mdq24 ad21 io gv dd ? memc_mdq25 af22 io gv dd ? memc_mdq26 ac21 io gv dd ? memc_mdq27 af21 io gv dd ? memc_mdq28 ae21 io gv dd ?
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 52 freescale semiconductor package and pin listings memc_mdq29 ad20 io gv dd ? memc_mdq30 af23 io gv dd ? memc_mdq31 ad22 io gv dd ? memc_mdm0 ac9 o gv dd ? memc_mdm1 ad5 o gv dd ? memc_mdm2 ae20 o gv dd ? memc_mdm3 ae22 o gv dd ? memc_mdqs0 ae8 io gv dd ? memc_mdqs1 ae5 io gv dd ? memc_mdqs2 ac19 io gv dd ? memc_mdqs3 ae23 io gv dd ? memc_mba0 ad16 o gv dd ? memc_mba1 ad17 o gv dd ? memc_mba2 ae17 o gv dd ? memc_ma0 ad12 o gv dd ? memc_ma1 ae12 o gv dd ? memc_ma2 af12 o gv dd ? memc_ma3 ac13 o gv dd ? memc_ma4 ad13 o gv dd ? memc_ma5 ae13 o gv dd ? memc_ma6 af13 o gv dd ? memc_ma7 ac15 o gv dd ? memc_ma8 ad15 o gv dd ? memc_ma9 ae15 o gv dd ? memc_ma10 af15 o gv dd ? memc_ma11 ae16 o gv dd ? memc_ma12 af16 o gv dd ? memc_ma13 ab16 o gv dd ? memc_mwe ac17 o gv dd ? memc_mras ae11 o gv dd ? memc_mcas ad11 o gv dd ? memc_mcs ac11 o gv dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 53 package and pin listings memc_mcke ad14 o gv dd 3 memc_mck af14 o gv dd ? memc_mck ae14 o gv dd ? memc_modt af11 o gv dd ? local bus controller interface lad0 n25 io ov dd 7 lad1 p26 io ov dd 7 lad2 p25 io ov dd 7 lad3 r26 io ov dd 7 lad4 r25 io ov dd 7 lad5 t26 io ov dd 7 lad6 t25 io ov dd 7 lad7 u25 io ov dd 7 lad8 m24 io ov dd 7 lad9 n24 io ov dd 7 lad10 p24 io ov dd 7 lad11 r24 io ov dd 7 lad12 t24 io ov dd 7 lad13 u24 io ov dd 7 lad14 u26 io ov dd 7 lad15 v26 io ov dd 7 la16 k25 o ov dd 7 la17 l25 o ov dd 7 la18 l26 o ov dd 7 la19 l24 o ov dd 7 la20 m26 o ov dd 7 la21 m25 o ov dd 7 la22 n26 o ov dd 7 la23 ac24 o ov dd 7 la24 ac25 o ov dd 7 la25 ab23 o ov dd 7 lcs0 ab24 o ov dd 4 table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 54 freescale semiconductor package and pin listings lcs1 ab25 o ov dd 4 lcs2 aa23 o ov dd 4 lcs3 aa24 o ov dd 4 lwe0 y23 o ov dd 4 lwe1 w25 o ov dd 4 lbctl v25 o ov dd 4 lale v24 o ov dd 7 cfg_reset_source[0]/lsda10/lgpl0 l23 io ov dd ? cfg_reset_source[1]/lsdwe /lgpl1 k23 io ov dd ? lsdras /lgpl2/loe j23 o ov dd 4 cfg_reset_source[2]/lsdcas /lgpl3 h23 io ov dd ? lgpl4/lgta /lupwait/lpbse g23 io ov dd 4, 8 lgpl5 ac22 o ov dd 4 lclk0 y24 o ov dd 7 lclk1 y25 o ov dd 7 duart uart_sout1/msrcid0 (ddr id)/lsrcid0 g1 io ov dd ? uart_sin1/msrcid1 (ddr id)/lsrcid1 g2 io ov dd ? uart_cts1 /msrcid2 (ddr id)/lsrcid2 h3 io ov dd ? uart_rts1 /msrcid3 (ddr id)/lsrcid3 k3 io ov dd ? uart_sout2/msrcid4 (ddr id)/lsrcid4 h2 io ov dd ? uart_sin2/mdval (ddr id)/ldval h1 io ov dd ? uart_cts2 j3 io ov dd ? uart_rts2 k4 io ov dd ? i 2 c interface iic_sda/ckstop_out ae24 io ov dd 2 iic_scl/ckstop_in af24 io ov dd 2 programmable interrupt controller mcp_out ad25 o ov dd ? irq0 /mcp_in ad26 i ov dd ? irq1 k1 io ov dd ? irq2 k2 i ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 55 package and pin listings irq3 j2 i ov dd ? irq4 j1 i ov dd ? irq5 ae26 i ov dd ? irq6 /ckstop_out ae25 io ov dd ? irq7 /ckstop_in af25 i ov dd ? cfg_clkin_div f1 i ov dd ? cfg_lbiu_mux_en m23 i ov dd ? jtag tck w26 i ov dd ? tdi y26 i ov dd 4 tdo aa26 o ov dd 3 tms ab26 i ov dd 4 trst ac26 i ov dd 4 test test_mode n23 i ov dd 6 pmc quiesce t23 o ov dd ? system control hreset ac23 io ov dd 1 poreset ad23 i ov dd ? sreset ad24 io ov dd 2 clocks clkin r3 i ov dd ? clkin p4 o ov dd ? pci_sync_out v1 o ov dd 3 rtc_pit_clock u23 i ov dd ? pci_sync_in/pci_clk v2 i ov dd ? pci_clk0/clkpd_cerisc1_ipg_clkout/dptc_osc t3 o ov dd ? pci_clk1/clkpd_half_cemb4ucc1_ipg_clkout/ clock_xlb_clock_out u2 o ov dd ? pci_clk2/clkpd_third_cesog_ipg_clkout/ cecl_ipg_ce_clock r4 o ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 56 freescale semiconductor package and pin listings power and ground supplies av dd 1p3iav dd 1? av dd 2 aa1 i av dd 2? av dd 3 ab15 i av dd 3? av dd 4c24iav dd 4? mvref1 ab8 i ddr reference voltage ? mvref2 ab17 i ddr reference voltage ? pci pci_inta /irq_out af2 o ov dd 2 pci_reset_out ae2 o ov dd ? pci_ad0/msrcid0 (ddr id) l1 io ov dd ? pci_ad1/msrcid1 (ddr id) l2 io ov dd ? pci_ad2/msrcid2 (ddr id) m1 io ov dd ? pci_ad3/msrcid3 (ddr id) m2 io ov dd ? pci_ad4/msrcid4 (ddr id) l3 io ov dd ? pci_ad5/mdval (ddr id) n1 io ov dd ? pci_ad6 n2 io ov dd ? pci_ad7 m3 io ov dd ? pci_ad8 p1 io ov dd ? pci_ad9 r1 io ov dd ? pci_ad10 n3 io ov dd ? pci_ad11 n4 io ov dd ? pci_ad12 t1 io ov dd ? pci_ad13 r2 io ov dd ? pci_ad14/ecid_tmode_in t2 io ov dd ? pci_ad15 u1 io ov dd ? pci_ad16 y2 io ov dd ? pci_ad17 y1 io ov dd ? pci_ad18 aa2 io ov dd ? pci_ad19 ab1 io ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 57 package and pin listings pci_ad20 ab2 io ov dd ? pci_ad21 y4 io ov dd ? pci_ad22 ac1 io ov dd ? pci_ad23 aa3 io ov dd ? pci_ad24 aa4 io ov dd ? pci_ad25 ad1 io ov dd ? pci_ad26 ad2 io ov dd ? pci_ad27 ab3 io ov dd ? pci_ad28 ab4 io ov dd ? pci_ad29 ae1 io ov dd ? pci_ad30 ac3 io ov dd ? pci_ad31 ac4 io ov dd ? pci_c_be0 m4 io ov dd ? pci_c_be1 t4 io ov dd ? pci_c_be2 y3 io ov dd ? pci_c_be3 ac2 io ov dd ? pci_par u3 io ov dd ? pci_frame w1 io ov dd 5 pci_trdy w4 io ov dd 5 pci_irdy w2 io ov dd 5 pci_stop v4 io ov dd 5 pci_devsel w3 io ov dd 5 pci_idsel p2 i ov dd ? pci_serr u4 io ov dd 5 pci_perr v3 io ov dd 5 pci_req0 ad4 io ov dd ? pci_req1 /cpci_hs_es ae3 i ov dd ? pci_req2 af3 i ov dd ? pci_gnt0 ad3 io ov dd ? pci_gnt1 /cpci_hs_led ae4 o ov dd ? pci_gnt2 /cpci_hs_enum af4 o ov dd ? m66en l4 i ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 58 freescale semiconductor package and pin listings ce/gpio gpio_pa0/ser1_txd[0]/tdma_txd[0]/usbtxn g3 io ov dd ? gpio_pa1/ser1_txd[1]/tdma_txd[1]/usbtxp f3 io ov dd ? gpio_pa2/ser1_txd[2]/tdma_txd[2] f2 io ov dd ? gpio_pa3/ser1_txd[3]/tdma_txd[3] e3 io ov dd ? gpio_pa4/ser1_rxd[0]/tdma_rxd[0]/usbrxp e2 io ov dd ? gpio_pa5/ser1_rxd[1]/tdma_rxd[1]/usbrxn e1 io ov dd ? gpio_pa6/ser1_rxd[2]/tdma_rxd[2]/usbrxd d3 io ov dd ? gpio_pa7/ser1_rxd[3]/tdma_rxd[3] d2 io ov dd ? gpio_pa8/ser1_cd/tdma_req/usboe d1 io ov dd ? gpio_pa9 tdma_clko c3 io ov dd ? gpio_pa10/ser1_cts/tdma_rsync c2 io ov dd ? gpio_pa11/tdma_strobe c1 io ov dd ? gpio_pa12/ser1_rts/tdma_tsync b1 io ov dd ? gpio_pa13/clk9/brgo9 h4 io ov dd ? gpio_pa14/clk11/brgo10 g4 io ov dd ? gpio_pa15/brgo7 j4 io ov dd ? gpio_pa16/ la0 (lbiu) k24 io ov dd ? gpio_pa17/ la1 (lbiu) k26 io ov dd ? gpio_pa18/enet2_txd[0]/ser2_txd[0]/ tdmb_txd[0]/la2 (lbiu) g25 io ov dd ? gpio_pa19/enet2_txd[1]/ser2_txd[1]/ tdmb_txd[1]/la3 (lbiu) g26 io ov dd ? gpio_pa20/enet2_txd[2]/ser2_txd[2]/ tdmb_txd[2]/la4 (lbiu) h25 io ov dd ? gpio_pa21/enet2_txd[3]/ser2_txd[3]/ tdmb_txd[3]/la5 (lbiu) h26 io ov dd ? gpio_pa22/enet2_rxd[0]/ser2_rxd[0]/ tdmb_rxd[0]/la6 (lbiu) c25 io ov dd ? gpio_pa23/enet2_rxd[1]/ser2_rxd[1]/ tdmb_rxd[1]/la7 (lbiu) c26 io ov dd ? gpio_pa24/enet2_rxd[2]/ser2_rxd[2]/ tdmb_rxd[2]/la8 (lbiu) d25 io ov dd ? gpio_pa25/enet2_rxd[3]/ser2_rxd[3]/ tdmb_rxd[3]/la9 (lbiu) d26 io ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 59 package and pin listings gpio_pa26/enet2_rx_er/ser2_cd/tdmb_req/ la10 (lbiu) e26 io ov dd ? gpio_pa27/enet2_tx_er/tdmb_clko/la11 (lbiu) f25 io ov dd ? gpio_pa28/enet2_rx_dv/ser2_cts/ tdmb_rsync/la12 (lbiu) e25 io ov dd ? gpio_pa29/enet2_col/rxd[4]/ser2_rxd[4]/ tdmb_strobe/la13 (lbiu) j25 io ov dd ? gpio_pa30/enet2_tx_en/ser2_rts/ tdmb_tsync/la14 (lbiu) f26 io ov dd ? gpio_pa31/enet2_crs/sdet la15 (lbiu) j26 io ov dd ? gpio_pb0/enet3_txd[0]/ser3_txd[0]/ tdmc_txd[0] a13 io ov dd ? gpio_pb1/enet3_txd[1]/ser3_txd[1]/ tdmc_txd[1] b13 io ov dd ? gpio_pb2/enet3_txd[2]/ser3_txd[2]/ tdmc_txd[2] a14 io ov dd ? gpio_pb3/enet3_txd[3]/ser3_txd[3]/ tdmc_txd[3] b14 io ov dd ? gpio_pb4/enet3_rxd[0]/ser3_rxd[0]/ tdmc_rxd[0] b8 io ov dd ? gpio_pb5/enet3_rxd[1]/ser3_rxd[1]/ tdmc_rxd[1] a8 io ov dd ? gpio_pb6/enet3_rxd[2]/ser3_rxd[2]/ tdmc_rxd[2] a9 io ov dd ? gpio_pb7/enet3_rxd[3]/ser3_rxd[3]/ tdmc_rxd[3] b9 io ov dd ? gpio_pb8/enet3_rx_er/ser3_cd/tdmc_req a11 io ov dd ? gpio_pb9/enet3_tx_er/tdmc_clko b11 io ov dd ? gpio_pb10/enet3_rx_dv/ser3_cts/ tdmc_rsync a10 io ov dd ? gpio_pb11/enet3_col/rxd[4]/ser3_rxd[4]/ tdmc_strobe a15 io ov dd ? gpio_pb12/enet3_tx_en/ser3_rts/ tdmc_tsync b12 io ov dd ? gpio_pb13/enet3_crs/sdet b15 io ov dd ? gpio_pb14/clk12 d9 io ov dd ? gpio_pb15 upc1_txaddr[4] d14 io ov dd ? gpio_pb16 upc1_rxaddr[4] b16 io ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 60 freescale semiconductor package and pin listings gpio_pb17/brgo1/ce_ext_req1 d10 io ov dd ? gpio_pb18/enet4_txd[0]/ser4_txd[0]/ tdmd_txd[0] c10 io ov dd ? gpio_pb19/enet4_txd[1]/ser4_txd[1]/ tdmd_txd[1] c9 io ov dd ? gpio_pb20/enet4_txd[2]/ser4_txd[2]/ tdmd_txd[2] d8 io ov dd ? gpio_pb21/enet4_txd[3]/ser4_txd[3]/ tdmd_txd[3] c8 io ov dd ? gpio_pb22/enet4_rxd[0]/ser4_rxd[0]/ tdmd_rxd[0] c15 io ov dd ? gpio_pb23/enet4_rxd[1]/ser4_rxd[1]/ tdmd_rxd[1] c14 io ov dd ? gpio_pb24/enet4_rxd[2]/ser4_rxd[2]/ tdmd_rxd[2] d13 io ov dd ? gpio_pb25/enet4_rxd[3]/ser4_rxd[3]/ tdmd_rxd[3] c13 io ov dd ? gpio_pb26/enet4_rx_er/ser4_cd/tdmd_req c12 io ov dd ? gpio_pb27/enet4_tx_er/tdmd_clko d11 io ov dd ? gpio_pb28/enet4_rx_dv/ser4_cts/ tdmd_rsync d12 io ov dd ? gpio_pb29/enet4_col/rxd[4]/ser4_rxd[4]/ tdmd_strobe d7 io ov dd ? gpio_pb30/enet4_tx_en/ser4_rts/ tdmd_tsync c11 io ov dd ? gpio_pb31/enet4_crs/sdet c7 io ov dd ? gpio_pc0/upc1_txdata[0]/ser5_txd[0] a18 io ov dd ? gpio_pc1/upc1_txdata[1]/ser5_txd[1] a19 io ov dd ? gpio_pc2/upc1_txdata[2]/ser5_txd[2] b18 io ov dd ? gpio_pc3/upc1_txdata[3]/ser5_txd[3] b19 io ov dd ? gpio_pc4/upc1_txdata[4] a24 io ov dd ? gpio_pc5/upc1_txdata[5] b24 io ov dd ? gpio_pc6/upc1_txdata[6] a23 io ov dd ? gpio_pc7/upc1_txdata[7] b26 io ov dd ? gpio_pc8/upc1_rxdata[0]/ser5_rxd[0] a21 io ov dd ? gpio_pc9/upc1_rxdata[1]/ser5_rxd[1] b20 io ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 61 package and pin listings gpio_pc10/upc1_rxdata[2]/ser5_rxd[2] b21 io ov dd ? gpio_pc11/upc1_rxdata[3]/ser5_rxd[3] a20 io ov dd ? gpio_pc12/upc1_rxdata[4] d19 io ov dd ? gpio_pc13/upc1_rxdata[5]/lsrcid0 c18 io ov dd ? gpio_pc14/upc1_rxdata[6]/lsrcid1 d18 io ov dd ? gpio_pc15/upc1_rxdata[7]/lsrcid2 a25 io ov dd ? gpio_pc16/upc1_txaddr[0] c21 io ov dd ? gpio_pc17/upc1_txaddr[1]/lsrcid3 d22 io ov dd ? gpio_pc18/upc1_txaddr[2]/lsrcid4 c23 io ov dd ? gpio_pc19/upc1_txaddr[3]/ldval d23 io ov dd ? gpio_pc20/upc1_rxaddr[0] c17 io ov dd ? gpio_pc21/upc1_rxaddr[1] d17 io ov dd ? gpio_pc22/upc1_rxaddr[2] c16 io ov dd ? gpio_pc23/upc1_rxaddr[3] d16 io ov dd ? gpio_pc24/upc1_rxsoc/ser5_cd a16 io ov dd ? gpio_pc25/upc1_rxclav d20 io ov dd ? gpio_pc26/upc1_rxprty/ce_ext_req2 e23 io ov dd ? gpio_pc27/upc1_rxen b17 io ov dd ? gpio_pc28/upc1_txsoc b22 io ov dd ? gpio_pc29/upc1_txclav/ser5_cts a17 io ov dd ? gpio_pc30/upc1_txprty a22 io ov dd ? gpio_pc31/upc1_txen/ser5_rts c20 io ov dd ? gpio_pd0/spimosi a2 io ov dd ? gpio_pd1/spimiso b2 io ov dd ? gpio_pd2/spiclk b3 io ov dd ? gpio_pd3/spisel a3 io ov dd ? gpio_pd4/spi_mdio/ce_mux_mdio a4 io ov dd ? gpio_pd5/spi_mdc/ce_mux_mdc b4 io ov dd ? gpio_pd6/clk8/brgo16/ce_ext_req3 f24 io ov dd ? gpio_pd7/gtm1_tin1/gtm2_tin2/clk5 g24 io ov dd ? gpio_pd8/gtm1_tgate1 /gtm2_tgate2 /clk6 h24 io ov dd ? gpio_pd9/gtm1_tout1 d24 io ov dd ? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 62 freescale semiconductor package and pin listings gpio_pd10/gtm1_tin2/gtm2_tin1/clk17 j24 io ov dd ? gpio_pd11/gtm1_tgate2 /gtm2_tgate1 b25 io ov dd ? gpio_pd12/gtm1_tout2 /gtm2_tout1 c4 io ov dd ? gpio_pd13/gtm1_tin3/gtm2_tin4/brgo8 d4 io ov dd ? gpio_pd14/gtm1_tgate3 /gtm2_tgate4 d5 io ov dd ? gpio_pd15/gtm1_tout3 a5 io ov dd ? gpio_pd16/gtm1_tin4/gtm2_tin3 b5 io ov dd ? gpio_pd17/gtm1_tgate4 /gtm2_tgate3 c5 io ov dd ? gpio_pd18/gtm1_tout4 /gtm2_tout3 a6 io ov dd ? gpio_pd19/ce_risc1_int/ce_ext_req4 b6 io ov dd ? gpio_pd20/clk18/brgo6 d21 io ov dd ? gpio_pd21/clk16/brgo5/upc1_clko c19 io ov dd ? gpio_pd22/clk4/brgo9/ucc2_clko a7 io ov dd ? gpio_pd23/clk3/brgo10/ucc3_clko b7 io ov dd ? gpio_pd24/clk10/brgo2/ucc4_clko a12 io ov dd ? gpio_pd25/clk13/brgo16/ucc5_clko b10 io ov dd ? gpio_pd26/clk2/brgo4/ucc1_clko e4 io ov dd ? gpio_pd27/clk1/brgo3 f4 io ov dd ? gpio_pd28/clk19/brgo11 d15 io ov dd ? gpio_pd29/clk15/brgo8 c6 io ov dd ? gpio_pd30/clk14 d6 io ov dd ? gpio_pd31/clk7/brgo15 e24 io ov dd ? power and ground supplies gv dd aa8, aa10, aa11, aa13, aa14, aa16, aa17, aa19, aa21, ab9, ab10, ab11, ab12, ab14, ab18, ab20, ab21, ac6, ac8, ac14, ac18 gv dd ?? ov dd e5, e6, e8, e9, e10, e12, e14, e15, e16, e18, e19, e20, e22, f5, f6, f8, f10, f14, f16, f19, f22, g22, h5, h6, h21, j5, j22, k21, k22, l5, l6, l22, m5, m22, n5, n21, n22, p6, p22, p23, r5, r23, t5, t21, t22, u6, u22, v5, v22, w22, y5, ab5, ab6, ac5 ov dd ?? table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 63 package and pin listings v dd k10, k11, k12, k13, k14, k15, k16, k17, l10, l17, m10, m17, n10, n17, p10, p17, r10, r17, t10, t17, u10, u11, u12, u13, u14, u15, u16, u17 v dd ?? v ss b23, e7, e11, e13, e17, e21, f11, f13, f17, f21, f23, g5, h22, k5, k6, l11, l12, l13, l14, l15, l16, l21, m11, m12, m13, m14, m15, m16, n6, n11, n12, n13, n14, n15, n16, p5, p11, p12, p13, p14, p15, p16, p21, r11, r12, r13, r14, r15, r16, r22, t6, t11, t12, t13, t14, t15, t16, u5, u21, v23, w5, w6, w21, w23, w24, y22, aa5, aa6, aa22, aa25, ab7, ab13, ab19, ab22, ac10, ac12, ac16, ac20 v ss ?? no connect nc c22 ? ? ? notes: 1. this pin is an open drain signal. a weak pull-up resistor (1 k ) should be placed on this pin to ov dd . 2. this pin is an open drain signal. a weak pull-up resistor (2?10 k ) should be placed on this pin to ov dd . 3. this output is actively driven during reset rather than being three-stated during reset. 4. these jtag and local bus pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull up if the chip is in pci host mode. follow the pci specification?s recommendation. 6. this pin must always be tied to gnd. 7.this pin has weak internal pull-down n-fet that is always enabled.8.though this pin has weak internal pull-up yet it is recommended to apply an external pull-up. table 55. mpc8323e pbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 64 freescale semiconductor clocking 22 clocking figure 43 shows the internal distribution of clocks within the mpc8323e. figure 43. mpc8323e clock subsystem the primary clock source for the mpc8323e can be one of two inputs, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode, respectively. core pll system lbc lclk[0:1] core_clk e300c2 core csb_clk to rest clkin csb_clk local bus pci_clk_out[0:2] pci_sync_out pci_clk/ clock unit of the device lbc_clk pci clock pci_sync_in memory device /n to local bus clock divider ( 2 ) 3 memc_mck memc_mck ddr ddr_clk ddr memory device pll to ddr memory controller clock cfg_clkin_div /2 divider divider 1 0 quicc pll engine ce_clk to quicc engine block mpc8323e crystal clkin
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 65 clocking 22.1 clocking in pci host mode when the mpc8323e is configured as a pci host device (rcwh[pcihost] = 1), clkin is its primary input clock. clkin feeds the pci clock divider ( 2) and the pci_sync_out and pci_clk_out multiplexors. the cfg_clkin_div configuration input selects whether clkin or clkin/2 is driven out on the pci_sync_out signal. pci_sync_out is connected externally to pci_sync_in to allow the internal clock subsystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_sync_in, with equal delay to all pci agent devices in the system. 22.1.1 pci clock outputs (pci_clk_out[0:2]) when the mpc8323e is configured as a pci host, it provides three separate clock output signals, pci_clk_out[0:2], for external pci agents. when the device comes out of reset, the pci clock out puts are disabled and are actively driven to a steady low state. each of the individual clock outputs can be enabled (enable toggling of the clock) by setting its corresponding occr[pcicoe n ] bit. all output clocks are phase-aligned to each other. 22.2 clocking in pci agent mode when the mpc8323e is configured as a pci agent device, pci_clk is the primary input clock. in agent mode, the clkin signal should be tied to gnd, and the clock output signals, pci_clk_out n and pci_sync_out, are not used. 22.3 system clock domains as shown in figure 43 , the primary clock input (frequency) is multiplied up by the system phase-locked loop (pll) and the clock unit to create three major clock domains: ? the coherent system bus clock ( csb_clk ) ? the quicc engine clock ( ce_clk ) ? the internal clock for the ddr controller ( ddr_clk ) ? the internal clock for the local bus controller ( lb_clk ) the csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = [pci_sync_in (1 + ~cfg_clkin_div )] spmf in pci host mode, pci_sync_in (1 + ~cfg_clkin_div ) is the clkin frequency. the csb_clk serves as the clock input to the e300c2 core. a second pll inside the core multiplies up the csb_clk frequency to create the internal clock for the core ( core_clk ). the system and core pll multipliers are selected by the spmf and corepll fields in the reset configuration word low (rcwl) which is loaded at power-on reset or by one of the hard-coded reset options. see the ?reset configuration? section in the mpc8323e powerquicc ii pro communications processor reference manual for more information.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 66 freescale semiconductor clocking the ce_clk frequency is determined by the quicc engine pll multiplication factor (rcwl[cepmf) and the quicc engine pll division factor (rcwl[cepdf]) according to the following equation: when clkin is the primary input clock, ce_clk = (primary clock input cepmf) (1 + cepdf) when pci_clk is the primary input clock, ce_clk = [primary clock input cepmf (1 + ~cfg_clkin_div)] (1 + cepdf) see the ?quicc engine pll multiplication factor ? section and the ?quicc engine pll division factor? section in the mpc8323e powerquicc ii pro communications processor reference manual for more information. the ddr sdram memory controller operates with a frequency equal to tw ice the frequency of csb_clk . note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the ddr clock divider ( 2) to create the differential ddr memory bus clock outputs (mck and mck ). however, the data rate is the same frequency as ddr_clk . the local bus memory controller operates w ith a frequency equal to the frequency of csb_clk . note that lbc_clk is not the external local bus frequency; lbc_clk passes through the lbc clock divider to create the external local bus clock output s (lsync_out and lclk[0:2]). the lbc clock divider ratio is controlled by lcrr[clkdiv]. see the ?lbc bus clock and clock ratios? section in the mpc8323e powerquicc ii pro communications processor reference manual for more information. in addition, some of the internal units may be require d to be shut off or operate at lower frequency than the csb_clk frequency. these units have a default clock ra tio that can be configured by a memory mapped register after the device comes out of reset. table 56 specifies which units ha ve a configurable clock frequency. refer to the ?system clock control register (sccr)? section in the mpc8323e powerquicc ii pro communications processor reference manual for a detailed description. note setting the clock ratio of these units must be performed prior to any access to them. table 57 provides the operating frequencies for the 8323e pbga under recommended operating conditions (see table 2 ). table 56. configurable clock units unit default frequency options security core, i2c, sap, tpr csb_clk off, csb_clk /2, csb_clk /3 pci and dma complex csb_clk off, csb_clk table 57. operating frequencies for pbga characteristic 1 max operating frequency unit e300 core frequency ( core_clk )333mhz coherent system bus frequency ( csb_clk )133mhz quicc engine frequency ( ce_clk )200mhz
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 67 clocking 22.4 system pll configuration the system pll is controlled by the rcwl[spmf] parameter. table 58 shows the multiplication factor encodings for the system pll. note system pll vco frequency = 2 (csb frequency) (system pll vco divider). the vco divider needs to be set properly so that the system pll vco frequency is in the range of 300?600 mhz. as described in section 22, ?clocking,? the lbcm, ddrcm, and spmf parameters in the reset configuration word low and the cfg_clkin_div configuration input signal select the ratio between the primary clock input (clkin or pci_clk) and the internal coherent system bus clock ( csb_clk ). table 59 ddr1/ddr2 memory bus frequency (mclk) 2 133 mhz local bus frequency (lclk n ) 3 66 mhz pci input frequency (clkin or pci_clk) 66 mhz 1 the clkin frequency, rcwl[spmf], and rcwl[corepll] settings must be chosen such that the resulting csb_clk , mclk, lclk[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2 the ddr1/ddr2 data rate is 2 the ddr1/ddr2 memory bus frequency. 3 the local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on lcrr[clkdiv]) which is in turn 1 or 2 the csb_clk frequency (depending on rcwl[lbcm]). table 58. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 reserved 0001 reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111?1111 reserved table 57. operating frequencies for pbga (continued) characteristic 1 max operating frequency unit
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 68 freescale semiconductor clocking shows the expected frequency values for the csb frequency for select csb_clk to clkin/pci_sync_in ratios. table 59. csb frequency options cfg_clkin_div_b at reset 1 1 cfg_clkin_div_b is only used for host mode; clkin must be tied low and cfg_clkin_div_b must be pulled up (high) in agent mode. spmf csb_clk : input clock ratio 2 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. input clock frequency (mhz) 2 25 33.33 66.67 csb_clk frequency (mhz) high 0010 2 : 1 133 high 0011 3 : 1 100 high 0100 4 : 1 100 133 high 0101 5 : 1 125 high 0110 6 : 1 high 0111 7 : 1 high 1000 8 : 1 high 1001 9 : 1 high 1010 10 : 1 high 1011 11 : 1 high 1100 12 : 1 high 1101 13 : 1 high 1110 14 : 1 high 1111 15 : 1 high 0000 16 : 1 low 0010 2 : 1 133 low 0011 3 : 1 100 low 0100 4 : 1 133 low 0101 5 : 1 low 0110 6 : 1 low 0111 7 : 1 low 1000 8 : 1 low 1001 9 : 1 low 1010 10 : 1 low 1011 11 : 1 low 1100 12 : 1 low 1101 13 : 1 low 1110 14 : 1 low 1111 15 : 1 low 0000 16 : 1
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 69 clocking 22.5 core pll configuration rcwl[corepll] selects the ratio between the internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). table 60 shows the encodings for rcwl[corepll]. corepll values not listed in table 60 should be considered reserved. note core vco frequency = core frequency vco divider vco divider (rcwl[corepll[0:1]]) must be set properly so that the core vco frequency is in the range of 500?800 mhz. table 60. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 0-1 2-5 6 nn 0000 n pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 11 0001 01:1 8 00 0001 11.5:1 2 01 0001 11.5:1 4 10 0001 11.5:1 8 11 0001 11.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 11 0010 02:1 8 00 0010 12.5:1 2 01 0010 12.5:1 4 10 0010 12.5:1 8 11 0010 12.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 11 0011 03:1 8
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 70 freescale semiconductor clocking 22.6 quicc engine pll configuration the quicc engine pll is controlled by the rcwl[cepmf] and rcwl[cepdf] parameters. table 61 shows the multiplication factor encodings for the quicc engine pll. the rcwl[cevcod] denotes the quicc engine pll vco internal frequency as shown in table 62 . note the vco divider (rcwl[cevcod]) must be set properly so that the quicc engine vco frequency is in the range of 300?600 mhz. the quicc engine frequency is not restrict ed by the csb and core frequencies. the csb, core, and quicc engine frequencies should be selected according to the performance requirements. the quicc engine vco frequency is derived from the following equations: ce_clk = (primary clock input cepmf) (1 + cepdf) quicc engine vco frequency = ce_clk vco divider (1 + cepdf) table 61. quicc engine pll multiplication factors rcwl[cepmf] rcwl[cepdf] quicc engine pll multiplication factor = rcwl[cepmf]/ (1 + rcwl[cepdf) 00000?00001 0 reserved 00010 0 2 00011 0 3 00100 0 4 00101 0 5 00110 0 6 00111 0 7 01000 0 8 01001?11111 0 reserved table 62. quicc engine pll vco divider rcwl[cevcod] vco divider 00 4 01 8 10 2 11 reserved
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 71 thermal 22.7 suggested pll configurations to simplify the pll configurations, the mpc8323e might be separated into two clock domains. the first domain contain the csb pll and the core pll. the core pll is connected serially to the csb pll, and has the csb_clk as its input clock. the second cl ock domain has the quicc engine pll. the clock domains are independent, and each of their plls are c onfigured separately. both of the domains has one common input clock. table 63 shows suggested pll configurations for 33, 25, and 66 mhz input clocks. 23 thermal this section describes the thermal specifications of the mpc8323e. 23.1 thermal characteristics table 64 provides the package thermal characteristics for the 516 27 27 mm pbga of the mpc8323e. table 63. suggested pll configurations conf no. spmf core pll cemf cedf input clock frequency (mhz) csb frequency (mhz) core frequency (mhz) quicc engine frequency (mhz) 1 0100 0000100 0110 0 33.33 133.33 266.66 200 2 0100 0000101 1000 0 25 100 250 200 3 0010 0000100 0011 0 66.67 133.33 266.66 200 4 0100 0000101 0110 0 33.33 133.33 333.33 200 5 0101 0000101 1000 0 25 125 312.5 200 6 0010 0000101 0011 0 66.67 133.33 333.33 200 table 64. package thermal characteristics for pbga characteristic board type symbol value unit notes junction-to-ambient natural convection single-layer board (1s) r ja 28 c/w 1, 2 junction-to-ambient natural convection four-layer board (2s2p) r ja 21 c/w 1, 2, 3 junction-to-ambient (@200 ft/min) single-layer board (1s) r jma 23 c/w 1, 3 junction-to-ambient (@200 ft/min) four-layer board (2s2p) r jma 18 c/w 1, 3 junction-to-board ? r jb 13 c/w 4 junction-to-case ? r jc 9c/w5
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 72 freescale semiconductor thermal 23.2 thermal management information for the following sections, p d = (v dd i dd ) + p i/o , where p i/o is the power dissipation of the i/o drivers. 23.2.1 estimation of junction temperature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + ( r ja p d ) where: t j = junction temperature ( c) t a = ambient temperature for the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. as a general statement, the value obtained on a single layer board is appropriate for a tightly packed pr inted-circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low pow er dissipation and the components are well separated. test cases have demonstrated that errors of a factor of two (in the quantity t j ? t a ) are possible. 23.2.2 estimation of junction temperature with junction-to-board thermal resistance the thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. the thermal performance of any component is strongly dependent on the power dissipation of surrounding components. in addition, the ambient temper ature varies widely within the application. for many natural convection and especially closed box a pplications, the board temperature at the perimeter junction-to-package top natural convection jt 2c/w6 notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 64. package thermal characteristics for pbga (continued) characteristic board type symbol value unit notes
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 73 thermal (edge) of the package is approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board te mperature provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, the junction temp erature is estimated using the following equation: t j = t b + ( r jb p d ) where: t j = junction temperature ( c) t b = board temperature at the package perimeter ( c) r jb = junction-to-board thermal resistance ( c/w) per jesd51-8 p d = power dissipation in package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the application board shoul d be similar to the thermal test condition: the component is soldered to a board with internal planes. 23.2.3 experimental determination of junction temperature to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top cente r of the package case using the following equation: t j = t t + ( jt p d ) where: t j = junction temperature ( c) t t = thermocouple temperature on top of package ( c) jt = thermal characterization parameter ( c/w) p d = power dissipation in package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 23.2.4 heat sinks and junction-to-case thermal resistance in some application environments, a heat sink is required to provide the necessary thermal management of the device. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance: r ja = r jc + r ca
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 74 freescale semiconductor thermal where: r ja = junction-to-ambient thermal resistance ( c/w) r jc = junction-to-case thermal resistance ( c/w) r ca = case-to-ambient thermal resistance ( c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface ma terial, the mounting arrangement on printed-circuit board, or change the thermal dissipation on th e printed-circuit board surrounding the device. to illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. the heat sink choice is determined by the application environment (temperature, air flow, adja cent component power dissipation) and the physical space available. because there is not a standard a pplication environment, a standard heat sink is not required. accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the c onduction cooling and the c onvection cooling of the air moving through the application. simplified thermal m odels of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. more detailed thermal models can be made available on request. heat sink vendors include the following list: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-567-8082 473 sapena ct. #12 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-thermal.com tyco electronics 800-522-2800 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 75 thermal wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com interface material vendors include the following: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials p.o. box 994 midland, mi 48686-0997 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 23.3 heat sink attachment when attaching heat sinks to these devices, an interface material is required. the best method is to use thermal grease and a spring clip. the spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. avoid attachment forces which would lift the edge of the package or peel the package from the board. such peeling forces reduce the solder joint lifetime of the package. recommended maximum force on th e top of the package is 10 lb (4.5 kg) force. if an adhesive attachment is planne d, the adhesive should be intended fo r attachment to painted or plastic surfaces and its performance verified under the application requirements. 23.3.1 experimental determination of the junction temperature with a heat sink when heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure th e heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 76 freescale semiconductor system design information interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. t j = t c + ( r jc p d ) where: t c = case temperature of the package ( c) r jc = junction-to-case thermal resistance ( c/w) p d = power dissipation (w) 24 system design information this section provides electrical and thermal design recommendations for successful application of the mpc8323e. 24.1 system clocking the mpc8323e includes three plls. ? the system pll (av dd 2 ) generates the system clock from th e externally supplied clkin input. the frequency ratio between the system and clkin is selected using the system pll ratio configuration bits as described in section 22.4, ?system pll configuration.? ? the e300 core pll (av dd 3 ) generates the core clock as a slave to the system clock. the frequency ratio between the e300 core clock and the system clock is selected using the e300 pll ratio configuration bits as described in section 22.5, ?core pll configuration.? ? the quicc engine pll (av dd 1 ) which uses the same reference as the system pll. the quicc engine block generates or uses external sources for all required serial interface clocks. 24.2 pll power supply filtering each of the plls listed above is provided with pow er through independent power supply pins. the voltage level at each av dd n pin should always be equivalent to v dd , and preferably these voltages are derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide five independent filter circuits as illustrated in figure 44 , one to each of the five av dd pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitors with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 77 system design information each circuit should be placed as cl ose as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd pin, which is on the periphery of pack age, without the inductance of vias. figure 44 shows the pll power supply filter circuit. figure 44. pll power supply filter circuit 24.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the mpc8323e can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc8323e system, and the mpc8323e itself requires a clean, tightly regulated s ource of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , and gv dd pins of the mpc8323e. these decoupling capacitors should receive their power from separate v dd , ov dd , gv dd , and gnd power planes in the pcb, utilizing short tr aces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , and gv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connect ed to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 24.4 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd , or gv dd as required. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd , ov dd , and gnd pins of the mpc8323e. 24.5 output buffer dc impedance the mpc8323e drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 45 ). the v dd av dd (or l2av dd ) 2.2 f 2.2 f gnd low esl surface mount capacitors (<0.5 nh) 10
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 78 freescale semiconductor system design information output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 45. driver impedance measurement the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the output voltage is measured while driving logic 1 without an external differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value r term . the measured voltage is v 2 =(1/(1/r 1 +1/r 2 )) i source . solving for the output impedance gives r source = r term (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . table 65 summarizes the signal impedance targets. the driver impedance are targeted at minimum v dd , nominal ov dd , 105 c. 24.6 configuration pin multiplexing the mpc8323e provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). these pins are generally used as output only pins in normal operation. table 65. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit r n 42 target 25 target 20 target z 0 w r p 42 target 25 target 20 target z 0 w differential na na na z diff w note: nominal supply voltages. see ta b l e 1 , t j = 105 c. ov dd ognd r p r n pad data sw1 sw2
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 79 ordering information while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. care ful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 24.7 pull-up resistor requirements the mpc8323e requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including i 2 c pins, ethernet management mdio pin, and ipic interrupt pins. for more information on required pull-up resistors and the connections required for the jtag interface, see an3361, ? mpc8321e/mpc8323e powerquicc design checklist,? rev. 1. 25 ordering information this section presents ordering information for the de vices discussed in this document, and it shows an example of how the parts are marked. ordering inform ation for the devices fully covered by this document is provided in section 25.1, ?part numbers fully addressed by this document.? 25.1 part numbers fully addressed by this document table 66 provides the freescale part numbering nomenclature for the mpc8323e family. note that the individual part numbers correspond to a maximum proc essor core frequency. for available frequencies, contact your local freescale sales office. in addition to the maximum processor core frequency, the part numbering scheme also includes the maximum eff ective ddr memory speed and quicc engine bus frequency. each part number also contains a revisi on code which refers to the die mask revision number. table 66. part numbering nomenclature mpc nnnn ec vrafdca product code part identifier encryption acceleration temperature range 1 package 2 e300 core frequency 3 ddr frequency quicc engine frequency revision level mpc 8323 blank = not included e = included blank = 0 to 105 c c = ?40 to 105 c vr = pb-free pbga zq = pb pbga ad = 266 mhz af = 333 mhz d = 266 mhz c = 200 mhz contact local freescale sales office notes: 1. contact local freescale office on availability of parts with c temperature r ange. 2. see section 21, ?package and pin listings,? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specifica tion support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 80 freescale semiconductor document revision history 25.2 part marking parts are marked as in the example shown in figure 46 . figure 46. freescale part marking for pbga devices 26 document revision history table 67 provides a revision history for this hardware specification. table 67. document revision history rev. no. date substantive change(s) 4 09/2010 ? replaced all instances of ?lccr? with ?lcrr? throughout. ? added footnotes 3 and 4 in table 2 , ?recommended operating conditions 3 .? ? modified section 8.1.1, ?dc electrical characteristics .? ? modified table 23 , ?mii transmit ac timing specifications.? ? modified table 24 , ?mii receive ac timing specifications.? ? added footnote 7 and 8, and modified some signal names in ta b l e 5 5 , ?mpc8323e pbga pinout listing.? 3 12/2009 ? removed references for note 4 from ta ble 1 . ? added figure 2 in section 2.1.2, ?power supply voltage specification . ? added symbol t a in ta b l e 2 . ? added footnote 2 in ta ble 2 . ? added a note in section 4, ?clock input timing for rise/fall time of qe input pins. ? modified clkin, pci_clk rise/fall time parameters in ta b l e 8 . modified min value of t mck in tab le 1 9 . ? modified figure 43 . ? modified formula for ce_clk calculation in section 22.3, ?system clock domains . ? added a note in section 22.4, ?system pll configuration . ? removed the signal ecid_tmode_in from ta b l e 5 5 . ? removed all references of rst signals from ta b l e 5 5 . mpcnnnnetppaaar core/platform mhz atwlyyww ccccc pbga *mmmmm ywwlaz notes : atwlyyww is the traceability code. ccccc is the country code. mmmmm is the mask number. ywwlaz is the assembly traceability code.
mpc8323e powerquicc ii pro integrated communications processor family hardware specifications, rev. 4 freescale semiconductor 81 document revision history 2 4/2008 ? removed figures 2 and 3 overshoot and undershoot voltage specs from section 2.1.2, ?power supply voltage specification ,? and footnotes 4 and 5 from ta ble 1 . ? corrected quiesce signal to be an output signal in ta b l e 5 5 . ? added column for gvdd (1.8 v) - ddr2 - to table 6 with 0.212-w typical power dissipation. ? added figure 4 ddr input timing diagram. ? removed ce_trb* and ce_pio* signals from ta b l e 5 5 . ? added three local bus ac specifications to tab le 3 0 (duty cycle, jitter, delay between input clock and local bus clock). ? added row in ta b l e 2 stating junction temperature range of 0 to 105?c. c. ? modified section 2.2, ?power sequencing ,? to include poreset requirement. 1 6/2007 correction to descriptive text in section 2.2. 0 6/2007 initial release. table 67. document revision history rev. no. date substantive change(s)
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